Design of Low Power and Power Scalable Pipelined ADC Using Current Modulated Power Scale

  • Dharmesh Kumar Pathak NRI Institute of Information Science & Technology, Bhopal, MP, India
  • Bakha Khambra NRI Institute of Information Science & Technology, Bhopal, MP, India
Keywords: Pipelined ADC, CMOS, low power, memory effect, opamp sharing, subsampling

Abstract

This work represents a power scalable pipelined ADC, which achieves low power variation depends upon the sampling rate and enables variation in throughput. The keys to power scalability at high sampling rates were current modulation-based architecture and the development of novel rapid power-on Op-amp, which can completely and quickly power on/off by the feedback approach. The result achieved in this design is as high as 50 Msps and as low as 1 ksps, keeping some important parameters of ADC as ENOB and SNDR are almost constant. Power variation in ADC has a flexible range from 7.5 µW to 17 mW, which is lower power consumption than previous works.

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References

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Published
2020-10-25
How to Cite
Pathak, D. K., & Khambra, B. (2020). Design of Low Power and Power Scalable Pipelined ADC Using Current Modulated Power Scale. International Journal of Advanced Computer Technology, 9(5), 16-20. Retrieved from http://www.ijact.org/index.php/ijact/article/view/63
Section
Articles